The present invention relates to a method for fabricating a semiconductor device, more specifically to a semiconductor device having a through-hole formed on the source/drain diffused layer of a MOS transistor by self-alignment with the gate electrode, and a method for fabricating the same.
As LSIs increase their scales, further micronization of the devices is sought. To realize further micronized semiconductor integrated circuits having gates, wirings, and through-holes of further micronized dimensions, exposure wavelengths of photolithography have been shortened to improve resolution.
While a minimum resolution dimension is thus made decreased, various device structures which allow alignment margins for alignment between lithography steps are studied, and an attempt is made to decrease device dimensions themselves without diminishing dimensions of patterns to be transferred.
Such a device structure is exemplified by self-aligned contact (hereinafter called SAC).
The conventional SAC will be explained with reference to FIG. 16.
A device isolation film 12 is formed on a silicon substrate 10, defining device regions 14 and 16. Gate electrodes 26 are formed on the silicon substrate in the device regions 14 and 16 through a gate oxide film 18. The gate electrodes 26 have their side walls and the top surfaces covered with an etching stopper film 36 of silicon nitride film. A source/drain diffused layer 28 is formed on the device regions 14 and 16 on both sides of the gate electrodes 26. MOS transistors comprising the gate electrodes 26, and the source/drain diffused layers 28 are thus formed.
An inter-layer insulation film 38, of e.g. BPSG (Boro-Phospho-Silicate Glass) film, formed on the silicon substrate 10 with the MOS transistors. In the inter-layer insulation film 38 there are formed through-holes 42, 44, and 48 exposing the source/drain diffused layer 28, and through-holes 46 exposes the gate electrodes 26. Of these through-holes 42 and 44 are the so-called SACs.
Then the method for forming the through-holes of SAC will be explained with reference to FIG. 17A.
After the MOS transistors having the gate electrodes 26 covered with the etching stopper film 36 are formed on the silicon substrate 10, the inter-layer insulation film 38 of BPSG film is formed.
Then a photoresist 40 having a pattern of the through-holes to expose the source/drain diffused layer 28, is formed; and with the photoresist 40 acting as a mask, the inter-layer insulation film 38 is etched.
At this time, the gate electrodes covered with the etching stopper film are present, in the regions that the through-holes 42 and 44 are formed into; however the etching stopper film 36 is not substantially etched when a sufficiently high selectivity ratio with respect to silicon nitride film as a condition for etching the inter-layer insulation film 38, is used. The through-holes 42 and 44 are able to expose the source/drain diffused layer 28 (FIG. 17A).
The through-holes 42 and 44, to expose the source/drain diffused layer 28, are thus formed in alignment with the position of the etching stopper film 36. This is why the through-holes 42 and 44 are called SACs.
The use of such an SAC structure allows the pattern of the through-holes 42 and 44 to be laid on the regions containing the gate electrodes 26. Even when the openings of the through-holes are a little displaced, the through-holes can be formed in alignment with the etching stopper film. Therefore, the alignment precision can be less strict.
Highly integrated semiconductor devices using SACs have thus been fabricated.
However, the above-described semiconductor device fabrication method using SACs cannot form the through-holes 46 which are to expose the gate electrodes concurrent with the through-holes 42, 44, and 48.
This limitation exists because, in the conventional SAC technique, when the through-holes 42, 44, 46, and 48 are concurrently formed by self-alignment using the silicon nitride film covering the gate electrodes 26 as the etching stopper film 36, the etching stopper film 36 covering the gate electrodes 26 adversely remains-in the through-holes 46 after the through-holes 42, 44, and 48, in which the source/drain diffused layer 28 is to be exposed, are formed.
Accordingly, to form the through-holes 46 exposing the gate electrodes 26, it is necessary to separately remove the etching stopper film 36. Thus, it is necessary to add one lithography step, as exemplified in FIG. 17B.